The problem addressed here is the accurate and efficient computation of reduced order macromodels for large and complex linear circuit models to be used in circuit simulation and/or timing verification. Interconnect and parasitic effects are pervasive in all types of designs including digital, analog, and mixed signal designs. The computational costs due to the size and complexity of these circuit models is a major bottleneck in the verification of these designs. Therefore, a technique to provide accurate and compact macromodels of these linear circuits will have a significant impact on overall design cycle time.
In the early 80's as clock rates steadily increased to the point where interconnect effects could no longer be ignored in digital designs, the RC tree method was developed to provide quick delay estimation for timing verification. This technique has limited applicability because of its specific nature. The need was ripe for a general method of efficient delay estimation for linear interconnect circuits, and the Asymptotic Waveform Evaluation (AWE) technique was developed to address that need. The trends in electronic circuit and system designs have continued to accentuate that need as well as other needs.
Two recent trends in integrated circuit designs have brought out the importance of interconnect and parasitic effects in design verification: the evolution towards submicron designs and the rapid growth of telecommunication/RF circuit designs. The combination of high frequencies and high packaging densities in these designs has quickly increased the size as well as the complexity of the linear circuit models for circuit simulation and timing verification.
Therefore, there is a need for a general tool to provide accurate and compact reduced order macromodeling of these linear circuit models to significantly improve the throughput of circuit simulation as well as timing verification, which in turn will improve the total design cycle time. In order to facilitate the discussion of different innovations that have been developed and applied to the problem of model reduction for circuit simulation and timing verification, various issue and problems are listed below:
1. Generality: The method must be able to handle general linear multiport circuits or networks. PA1 2. Flexibility: The method must be able to provide models of variable accuracy as required by a given problem. PA1 3. Accuracy: The method must be able to provide accurate approximations or reduced order models over a wide range of frequency both in frequency and in the time domain if necessary. PA1 4. Efficiency: The method needs to provide as compact a reduced model as possible for simulation/verification efficiency. PA1 (a) Unnecessary high order approximations (loss of compactness) due to the scalar nature of the underlying algorithm (one port at a time), PA1 (b) Unnecessary high order approximations due to expansion about a single frequency, and PA1 (c) stability of the reduced model.
Three different prior art approaches are discussed below. The first include explicit moment matching techniques. The AWE technique was developed initially as a general technique to compute reduced order models of linear lumped circuits. This technique was later improved to handle distributed circuits. Two different implementations of the AWE technique have been patented (see U.S. Pat. No. 5,313,398 and U.S. Pat. No. 5,379,231). AWE was the first major application of explicit moment matching techniques for computing partial Pade approximations to the simulation of large interconnect circuits. One problem with this type of technique is the loss of numerical precision as the order of the approximation is increased. This problem limits the applicability of AWE in terms of approximations such as pole/zero analysis of analog circuits and transmission line modeling where high accuracy, i.e., high order approximation, is required. Complex Frequency Hopping (CFH) and multipoint Pade techniques have been developed to address the numerical precision problems of AWE. These techniques alleviate the numerical precision problem of AWE and allow higher order approximations to be computed. However, these problems are not completely solved by CFH and multipoint Pade techniques because both are still explicit moment matching methods. The loss of numerical precision for high order approximations is inherent in explicit moment matching techniques. In addition, these two techniques also incur significantly more computational cost than AWE, thus losing the key efficiency advantage of AWE.
The second approach includes the use of scaler Lanczos base algorithms. Scaler Lanczos techniques address the numerical precision problem described above. They are as efficient as AWE while allowing very high order approximations to be computed accurately. The remaining problems that affect the overall efficiency and accuracy of simulation and verification are enumerated below for the convenience of discussion:
Problem (a) is also inherent in the techniques described in AWE above. The scalar Lanczos based techniques have been extended to the block version to address this problem. These techniques are described in the Block Lanczos algorithms below. No block (multiport) version of the techniques described in AWE have been developed or reported. Problem (c) is related to problem (b) in the sense that too high an approximation around one expansion frequency may not ensure the stability of the reduced model. Rational Lanczos algorithms are developed to compute multipoint partial Pade approximations, i.e., approximations about multiple expansion frequency points. These techniques address problems (b) and (c), but do not address problem (a).
The third potential solution is the use of Block Lanczos algorithms. These techniques have been used to address problem (a) above by taking into account the interaction among ports to improve compactness of the reduced model. The scalar algorithm just processes one port at a time and does not take into account their interaction, thus not allowing common information to be shared by the approximation for each port. Problems (b) and (c) are not addressed by the Block Lanczos algorithms.